Exemplary embodiments relate to a nonvolatile memory device and a method of operating the same and, more particularly, to a nonvolatile memory device and a method of operating the same, which are capable of prohibiting malfunction of an operation for sensing the voltage level of a bit line due to a source bouncing phenomenon.
In recent years, there has been an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and which do not require the refresh function of rewriting data at specific intervals. To develop a high capacity of a memory device capable of storing a large amount of data, technology for the high degree of integration of memory cells is being developed.
To increase the degree of integration of memory cells, a NAND type flash memory device in which a number of the memory cells are coupled in series to form one cell string and two cell strings share one contact has been developed. In such a NAND type flash memory device, program and erase operations are performed by controlling the threshold voltage of a memory cell while injecting or discharging electrons into or from a floating gate according to F-N tunneling.
Accordingly, an erased memory cell has a negative threshold voltage because electrons are discharged from a floating gate. A programmed memory cell has a positive threshold voltage because electrons are injected into a floating gate. However, the NAND type flash memory device has defects resulting from a charge gain or the loss of charges, and so several verification operations are performed on the memory device in relation to such characteristics. Here, a page buffer is used to verify whether the program and erase operations have normally been performed.
The above-described flash memory device performs a program operation by controlling the voltage level of a bit line coupled to a memory cell using the page buffer and performing a read operation or a program verification operation by sensing the voltage level of the bit line.
The known flash memory device includes a number of the memory cells and performs the read or program verification operation on the memory cells coupled to a number of the bit lines. Accordingly, some of the bit lines precharged to a high voltage level have to be discharged to a low voltage level 0 V in response to program states. However, if current flowing through a number of the bit lines is discharged to the source line, a source bouncing phenomenon is generated. Consequently, error can occur during the read or program verification operation because the bit lines, that have to be discharged to a low voltage level, are not fully discharged.